1. Field of the Invention
The invention relates to the field of semiconductor devices and, more particularly, to multi-chip packages and a method of forming such packages.
2. Description of the Related Art
In light of new developments in semiconductor technology and user demands, the electronics industry has been engaged in continuing efforts towards reducing the size, weight and power consumption of semiconductor devices. One technique utilized in these efforts is multi-chip packages (MCPs) in which a plurality of semiconductor chips are mounted in a single package.
Generally, MCPs utilize one of two main structural configurations, i.e., a chip stacking configuration or a parallel arrangement configuration. Chip stacking configurations may introduce difficulties associated with a more complex manufacturing process and complications or limitations associated with increased package thickness. Parallel arrangement configurations, while reducing some of the issues associated with chip stacking configurations, are generally more limited in their ability to reduce the overall size of the resulting package.
FIG. 1 is a cross-sectional view of a conventional stacked MCP. As illustrated in FIG. 1, the conventional MCP 210 has a first chip 211 and a second chip 213 attached on the lower and upper surfaces of a leadframe pad 221 with adhesive layers 231 and 235, respectively. The leadframe pad 221 may include a recess formed in the upper surface for receiving chip 213 that will tend to reduce the overall thickness of the package 210. The first and second chips 211 and 213 are electrically connected to inner leads 223 through bonding wires 241 and 243. The first chip 211, the second chip 213 and the bonding wires 241 and 243 may then be sealed by a package body 251 in order to protect them from the external environment. Outer leads 225 are typically formed integrally with and electrically connected to the inner leads 223 and extend from the package body for the purpose of making external connections. The package body 251 may typically be formed from a conventional epoxy molding compound (EMC) or other suitable polymeric material.
A MCP as illustrated in FIG. 1 that combines two chips in a single package will tend to reduce the mounting area required when compared with two packages each having a single chip. However, the conventional process of manufacturing such a MCP requires a series of sequential steps, such as a first chip attaching step, a second chip attaching step, a first wire-bonding step and a second wire-bonding step, etc.
Because some of these steps must be performed on both sides of the leadframe, the leadframe will typically be inverted repeatedly during the process, increasing the risk of damage to structures arranged on the opposite side such as the first chip and/or the bond wires attaching the first chip to the leadframe. Further, because the surface opposite the active surface of the first chip is attached to the leadframe pad, the MCP design must allow sufficient height for the bond wire loops above the active surface, thereby increasing the package thickness. Furthermore, reducing the thickness of the mounting portion of the leadframe in order to reduce the overall thickness of the resulting device increases the complexity of forming the leadframe and increases the likelihood of mechanical failures and/or reliability issues associated with the reduced leadframe pad thickness.